As communication speeds have increased, the demands to transmit signals over existing infrastructures have become significantly harder to meet. Four twisted pair Ethernet cabling, originally conceived for conveying signals at 1 or 10 Mb/s, is now required to convey signals at rates of the order of 1 Gb/s. Inter alia, the increased throughput leads to increased processing requirements for received signals as well as increased impairment of the received signals.
An IEEE standard 802.3ab, published by the Institute of Electronic and Electrical Engineers, New York, N.Y., describes an Ethernet protocol wherein data may be transmitted as five-level pulse amplitude modulation (PAM-5) signals over category-5 cables, comprising four pairs of twisted wires. The data may be transmitted in a full-duplex mode at rates of the order of 1 Gb/s. As in most data transmission systems, signal degradation along a transmission path means that signal recovery becomes increasingly more difficult as the path length increases, and/or as the rate of transmission increases. In particular, recovering the clocks for such degraded signals is a significant problem as signal frequencies increase, both because of the increased degradation of the signals and also because of the reduced time available for processing the signals.
In a paper by Mueller and Muller, “Timing recovery in digital synchronous data receivers,” IEEE Transactions on Communications, pp 516–531, Vol. 24, May 1976, the authors propose a timing recovery algorithm. The paper is accepted in the art as the basis for timing recovery algorithms, and relies on selecting a timing function of a best sampling point. The phase of the sampling point is then adjusted until its timing function is zero.
U.S. Pat. No. 6,192,072, to Azadet et al., whose disclosure is incorporated herein by reference, describes a parallel processing decision feedback equalizer (DFE) which may be applied to recovering the clocks from IEEE 802.3ab signals transmitted on four pairs of wires. The method relies on multiple clock domains, respective clock recovery being performed on each pair of wires.
With the increase of data speeds, receivers operating at the increased frequencies increasingly suffer from extraneous noise introduced into the data transmission lines. The receivers require filters to reduce the effects of such noise. However, filters known in the art occupy considerable chip area, and also consume significant amounts of power.
Transmitting signals over more than one line inherently incurs the risk that the received signals may be skewed, i.e., that signals which are transmitted simultaneously are received at different times. The time difference between the lines is termed the skew of the signal, and the skew must first be corrected before the original signal can be recovered. (IEEE standard 802.3ab states that for systems operating under the standard the skew shall not exceed 50 ns.) Typically, methods known in the art for correcting the skew rely on a trial and error approach. An originally matched set of symbols from a transmitter is received on different lines, and different delays are inserted into each of the lines until the received symbols match. However, using this method consumes considerable time before the skew is determined.
A further problem in determining skew is that the receiver may not know exactly which matched symbols are transmitted. For example, IEEE standard 802.3ab defines a variable loc_rcvr_status, which flags whether the status of an overall receive link is satisfactory or not. The matched symbols from the transmitter differ depending on the value of loc_rcvr_status. If the receiver does not know which value of loc_rcvr_status the transmitter is using, the receiver must test for both situations; if a trial and error approach is used the time before the skew is determined is further lengthened.